Computer Organization
- tags
- Operating Systems
Pipelining
- Increases throughput, but not latency
Structural Hazard
Data Hazard
- Resolved with extra hardware
Control Hazard
- Branch instructions need to tell which branch, but have only just read from memory
- Branch prediction (static/dynamic)
Pipelined Datapath and Control
- IF: Instruction Fetch
- ID: Instruction Decode and register file read
- EX: Execution or address calculation
- MEM: Data memory access
- WB: Write Back
Issues
- Write-back stage places the result back into the register file in the middle of the data path (Data Hazard)
- Selection of the next value of the PC, between incremented PC and branch address from the MEM stage (Control Hazard)
Data flow does not affect current instruction, but only influence later instructions.